While the trend of integrating complex electronic systems in an integrated circuit (IC) continues, there is an increasing demand for high-performance memory devices for storing software programs and processed data. As a reliable, proven technology, a Static Random Access Memory (SRAM) is the instinctive choice of a high-performance stand-alone memory device or an embedded memory device used in ICs having a system-on-a-chip (SOC) configuration. The distinct advantages of an SRAM include fast access speed, low power consumption, high noise margin, and process compatibility with a conventional CMOS fabrication process, among others. There is a continuous quest for SRAMs with higher storage cell density so that a larger amount of data can be stored.
FIG. 1A shows a schematic diagram of a conventional six transistor CMOS SRAM cell 5. In SRAM cell 5, a first inverter 2, comprising a first pull-up PMOS transistor P1 and a first pull-down NMOS transistor N1, is cross-coupled with a second inverter 4, comprising a second pull-up PMOS transistor P2 and a second pull-down NMOS transistor N2. The source, drain and gate of each transistor are labeled with an “S,” “D,” or “G,” respectively. The gate electrodes of P1 and N1 and the source regions of P2 and N2 make up a first storage node “A.” The gate electrodes of P2 and N2 and the source regions of P1 and N1 make up a second storage node “B.” The drains of P1 and P2 and the drains of N1 and N2 are coupled to a supply voltage VDD and ground GND, respectively.
During operation, data is written into the SRAM cell 5 by first activating the wordline WL coupled to access NMOS transistors N3 and N4. Subsequently, the digital bit carried on the bitline BL will be passed to the storage node “B” and the complementary bit on the bitline BL will be passed to the storage node “A.” This state will be held until new data is applied on the access transistors N3 and N4.
Due to the inherently lower carrier mobility of holes than that of electrons, a PMOS transistor in an SRAM cell is typically formed occupying larger silicon surface than that of an NMOS transistor in order to obtain matching drive currents between an NMOS and a PMOS transistor, generally leading to the desired symmetric device electrical characteristics. This situation may slow down the pace of continuously scaling-down device feature sizes and increasing memory cell density in an SRAM.
FIG. 1B illustrates a portion of the cross sectional view of CMOS SRAM cell 5, where strain engineering is employed to enhance PMOS transistors P1 and P2 performance in SRAM cell 5. This is accomplished by etching a recess into silicon substrate 10 at the source/drain regions of P1 and P2. Relaxed silicon germanium (SiGe) epitaxial layer 12 is then selectively grown in the source region “S” and drain region “D” of P1 and P2. Because the lattice constant of the SiGe is greater than that of silicon, the channel regions “C” between the SiGe source/drains of P1 and P2 are placed under compressive stresses, leading to a significant drive current increase for P1 and P2. However, due to the lateral extension of SiGe epitaxial layer 12 during the epitaxial growth process, SiGe from drain region “D” of P1 and SiGe from source region “S” of P2 may bridge a shallow trench isolation (STI) isolating P1 and P2, thereby electrically shorting drain region “D” of P1 and source region “S” of P2. This problem prevents forming thick SiGe epitaxial layer that typically provides favorable electrical characteristics, such as reduced contact resistance. This problem may also lead to reduced SRAM cell manufacturing yield.